While not perhaps the most interesting topic for some, this is a post I have been meaning to do for some time, and the recent Intel E5-2600v2 CPU Additions into the Cisco UCS lineup have kicked my butt into writing this post.
Like most blogs, this site started off purley as an online respositpory for my own reference, and if the infomation helped someone else, then hey happy days.
One of the most enjoyable aspects of my job is training internal staff and external customers, and as such not only am I required to have good practical skills but also good classroom theory.
In every Cisco UCS Course I deliver, I always give a session on Intel processor architecture and how the Intel CPU’s have evolved and how that evolution matches into the Cisco UCS product line.
In the “old days” this was easy; an M1 Blade = Intel XEON 5500 (Nehalem) and an M2 Blade = Intel XEON 5600 (Westmere), then came the Nehalem EX (6500/7500) the Westmere EX (E7-2800 and E7-4800) , the Sandy Bridge E5′s and now the Ivy Bridge E5′s. And with all these numbers and codenames flying around it is no surprise that people can get a bit confused.
This prompted me to knock up a nice little “Crib Sheet” on what processors are used in what models along with their codename and official launch name designators.
Intels Processor evolution happens in two steps a “Tock” which is a microarchitecture change and then a “Tick” which is the same microarchitecture only made smaller. For example the Cisco UCS journey began using the Nehalem Microarchitecture “Tock” on a 45nm High-K Process, then came the Westmere “Tick” where the process was shrunk to give us the same Nehalem Microarchitecture but this time on a 32nm High-K process. This reduction in process size usually is coupled with an increase in core count due to the fact that as the technology is made smaller, Intel can fit more cores onto the die.
Intel also have certain “Segments” or types of CPU’s which are EN, EP and EX
EN = Entry Level (Used in B22M3)
EP = Efficient Performance (2 Socket)
EX = Expanded (up to 4 Socket with Expanded memory architecture)
So all the above leads nicely into the below crib sheet. which details the Microarchitecture, Process Size, The Cisco UCS Server it is used in, and the Maximum Core/Memory it can support.